1  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    2  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    3  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    4  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    5  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    6  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    7  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    8  05:27:12.808464432 unknown CHDLC protocol (0x3030)
    9  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   10  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   11  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   12  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   13  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   14  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   15  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   16  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   17  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   18  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   19  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   20  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   21  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   22  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   23  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   24  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   25  05:27:12.808464432 unknown CHDLC protocol (0x3030)
   26  05:27:12.808464432  [|chdlc]