cat3 src1 and src2, some parts are similar to cat2/cat4 src encoding, but a few extra bits trimmed out to squeeze in the 3rd src register (dropping (abs), immed encoding, and moving a few other bits elsewhere) {HALF}{SRC} 00000 src {IMMED_ENCODING} {IMMED} 1 {HALF}c{CONST}.{SWIZ} 10 src->num >> 2 src->num & 0x3 src->uim_val 01 src->array.offset {HALF}r<a0.x + {OFFSET}> 0 {HALF}c<a0.x + {OFFSET}> 1 {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1}, {SRC2_NEG}{HALF}{SRC2}, {SRC3_NEG}{SRC3} {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1_R}{SRC1}, {SRC2_NEG}{SRC2_R}{HALF}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3} The source precision is determined by the instruction opcode. If {DST_CONV} the result is widened/narrowed to the opposite precision. 011 !!(src->srcs[0]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)) extract_SRC1_R(src) extract_SRC2_R(src) !!(src->srcs[2]->flags & IR3_REG_R) !!(src->srcs[1]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)) !!(src->srcs[2]->flags & (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT)) src->srcs[0] ((src->dsts[0]->num >> 2) == 62) ? 0 : !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) 0 The difference is that this cat3 version does not support plain const registers as src1/src3 but does support inmidiate values. On the other hand it still supports relative gpr and consts. 1 src->srcs[2] false (src2 << src1) | src3 1011 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111